//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/* Copyright 2001 Intel Corp.  */
/*++

Module Name:  $Workfile: BVD_UDC_Bits.h $

Abstract:
  Contains macro definitions for the USB Device Controller
  Registers bit manipulation

Functions:


Notes:

--*/

#ifndef __BSPUDCBITS_H__
#define __BSPUDCBITS_H__

#define __BSPREG(x)    (*(volatile unsigned long*)(x))

/* GPIO registers */

#define GPLR0       __BSPREG(0x80E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1       __BSPREG(0x80E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2       __BSPREG(0x80E00008)  /* GPIO Pin-Level Register GPIO<95:64> */

#define GPDR0       __BSPREG(0x80E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1       __BSPREG(0x80E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2       __BSPREG(0x80E00014)  /* GPIO Pin Direction Register GPIO<95:64> */

#define GPSR0       __BSPREG(0x80E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1       __BSPREG(0x80E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2       __BSPREG(0x80E00020)  /* GPIO Pin Output Set Register GPIO<95:64> */

#define GPCR0       __BSPREG(0x80E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1       __BSPREG(0x80E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2       __BSPREG(0x80E0002C)  /* GPIO Pin Output Clear Register GPIO <95:64> */

#define GRER0       __BSPREG(0x80E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1       __BSPREG(0x80E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2       __BSPREG(0x80E00038)  /* GPIO Rising-Edge Detect Register GPIO<95:64> */

#define GFER0       __BSPREG(0x80E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1       __BSPREG(0x80E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2       __BSPREG(0x80E00044)  /* GPIO Falling-Edge Detect Register GPIO<95:64> */

#define GEDR0       __BSPREG(0x80E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1       __BSPREG(0x80E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2       __BSPREG(0x80E00050)  /* GPIO Edge Detect Status Register GPIO<95:64> */

#define GAFR0_L     __BSPREG(0x80E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U     __BSPREG(0x80E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L     __BSPREG(0x80E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U     __BSPREG(0x80E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L     __BSPREG(0x80E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U     __BSPREG(0x80E00068)  /* GPIO Alternate Function Select Register GPIO <95:80> */
#define GAFR3_L     __BSPREG(0x80E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U     __BSPREG(0x80E00070)  /* GPIO Alternate Function Select Register GPIO <120:112> */

#define GPLR3       __BSPREG(0x80E00100)  /* GPIO Pin-Level Register GPIO<120:96> */
#define GPDR3       __BSPREG(0x80E0010C)  /* GPIO Pin Direction Register GPIO<120:96> */
#define GPSR3       __BSPREG(0x80E00118)  /* GPIO Pin Output Set Register GPIO<120:96> */
#define GPCR3       __BSPREG(0x80E00124)  /* GPIO Pin Output Clear Register GPIO <120:96> */
#define GRER3       __BSPREG(0x80E00130)  /* GPIO Rising-Edge Detect Register GPIO<120:96> */
#define GFER3       __BSPREG(0x80E0013C)  /* GPIO Falling-Edge Detect Register GPIO<120:96> */
#define GEDR3       __BSPREG(0x80E00148)  /* GPIO Edge Detect Status Register GPIO<120:96> */

#define RCNR_SEC    __BSPREG(0x80900000)  /* Second Uint Timer */
#define OSCR_SEC    __BSPREG(0x80A00010)

#define ICMR      __BSPREG(0x80D00004) /* Interrupt Controller Mask Registers */
#define INTC_USBCLIENT  (0x1u << 11)

#define CKEN      __BSPREG(0x81300004)  /* Clock Enable Register */
#define CKEN11_USB  (1 << 11)   /* USB Unit Clock Enable */
// Masks for UDC Registers

#define UDCWAKEUP    __BSPREG(0x80F00044)
#define UP2OCR       __BSPREG(0x80600020)
// UDC Control Register Macros (UDCCR)
//
#define UDCCR     __BSPREG(0x80600000)

#define UDCICR0   __BSPREG(0x80600004)
#define UDCICR1   __BSPREG(0x80600008)
#define UDCISR0   __BSPREG(0x8060000C)
#define UDCISR1   __BSPREG(0x80600010)

#define UDCCSR0   __BSPREG(0x80600100)
#define UDCCSRA   __BSPREG(0x80600104)
#define UDCCSRB   __BSPREG(0x80600108)
#define UDCCSRC   __BSPREG(0x8060010C)

#define UDCBCR0   __BSPREG(0x80600200)
#define UDCBCRA   __BSPREG(0x80600204)
#define UDCBCRB   __BSPREG(0x80600208)
#define UDCBCRC   __BSPREG(0x8060020C)

#define UDCDR0    __BSPREG(0x80600300)
#define UDCDRA    __BSPREG(0x80600304)
#define UDCDRB    __BSPREG(0x80600308)
#define UDCDRC    __BSPREG(0x8060030C)

#define UDCCRA    __BSPREG(0x80600404)
#define UDCCRB    __BSPREG(0x80600408)
#define UDCCRC    __BSPREG(0x8060040C)

//UDC MASK REG
#define UDC_WRITE(x, y) ((x) |= (y))
#define UDC_MASK(x, y)  ((x) &= ~(y))
#define UDC_ISRCLR(x, y)((x) = (y))
// UDC Control Register (UDCCR)
#define UDCCR_UDE      ( 0x1U << 0 ) // UDC enabled
#define UDCCR_UDA      ( 0x1U << 1 ) // READ-ONLY: udc is active
#define UDCCR_UDR      ( 0x1U << 2 ) // Forces the usb out of suspend state
#define UDCCR_EMCE     ( 0x1U << 3 ) // The Endpoint memory config. has an error
#define UDCCR_SMAC     ( 0x1U << 4 ) // Switch Endpoint memory to Active config.
                                            // Active interface and Alternate Interface
#define UDCCR_AAISN_SHIFT  5                // Shift and a mask for the Alternate Interface
#define UDCCR_AAISN_MASK   ( 0x7U << UDCCR_AAISN_SHIFT )  // Settings  (0-7)
#define UDCCR_AIN_SHIFT    8               // Shift and a mask for the Interface
#define UDCCR_AIN_MASK     ( 0x7U << UDCCR_AIN_SHIFT )    // Number    (0-7)
#define UDCCR_ACN_SHIFT    11              // Shift and a mask for the Configuration
#define UDCCR_ACN_MASK     ( 0x3U << UDCCR_ACN_SHIFT )    // Number    (0-3)
#define UDCCR_DRWF     ( 0x1U << 16 ) // Device Remote Wakeup Feature

// UDC Interrupt Control Register 0 (UDCICR0)
#define UDCICR0_IE0_0  ( 0x1U << 0 ) // Packet Complete Interrupt Enable - Endpoint 0
#define UDCICR0_IE0_1  ( 0x1U << 1 )   // FIFO Error Interrupt Enable - Endpoint 0
#define UDCICR0_IEA_0  ( 0x1U << 2 ) // Packet Complete Interrupt Enable - Endpoint A
#define UDCICR0_IEA_1  ( 0x1U << 3 )   // FIFO Error Interrupt Enable - Endpoint A
#define UDCICR1_IERS   ( 0x1U << 27 )  // Interrupt Enable - Reset
#define UDCICR1_IESU   ( 0x1U << 28 )  // Interrupt Enable - Suspend
#define UDCICR1_IERU   ( 0x1U << 29 )  // Interrupt Enable - Resume
#define UDCICR1_IESOF  ( 0x1U << 30 )  // Interrupt Enable - SOF
#define UDCICR1_IECC   ( 0x1U << 31 )  // Interrupt Enable - Configuration Change

// UDC Interrupt Status Register 0 (UDCICR0)
#define UDCISR0_IR0_0  ( 0x1U << 0 ) // Packet Complete Interrupt Request - Endpoint 0
#define UDCISR0_IR0_1  ( 0x1U << 1 )   // FIFO Error Interrupt Request - Endpoint 0
#define UDCISR0_IRA_0  ( 0x1U << 2 ) // Packet Complete Interrupt Request - Endpoint A
#define UDCISR0_IRA_1  ( 0x1U << 3 )   // FIFO Error Interrupt Request - Endpoint A
#define UDCISR0_IRB_0  ( 0x1U << 4 ) // Packet Complete Interrupt Request - Endpoint B
#define UDCISR0_IRB_1  ( 0x1U << 5 )   // FIFO Error Interrupt Request - Endpoint B
#define UDCISR0_IRC_0  ( 0x1U << 6 ) // Packet Complete Interrupt Request - Endpoint C
#define UDCISR0_IRC_1  ( 0x1U << 7 )   // FIFO Error Interrupt Request - Endpoint C

// UDC Interrupt Status Register 1 (UDCICR1)
#define UDCISR1_IRRS  ( 0x1U << 27 )  // Interrupt Request - Reset
#define UDCISR1_IRSU  ( 0x1U << 28 )  // Interrupt Request - Suspend
#define UDCISR1_IRRU  ( 0x1U << 29 )  // Interrupt Request - Resume
#define UDCISR1_IRSOF ( 0x1U << 30 )  // Interrupt Request - SOF
#define UDCISR1_IRCC  ( 0x1U << 31 )  // Interrupt Request - Configuration Change

// UDC Endpoint 0 Control/Status Register (UDCCSR0)
#define UDCCSR0_OPR  ( 0x1U << 0 ) // OUT packet to endpoint zero received
#define UDCCSR0_IPR  ( 0x1U << 1 ) // Packet has been written to endpoint zero FIFO
#define UDCCSR0_FTF  ( 0x1U << 2 ) // Flush the Tx FIFO
#define UDCCSR0_SST  ( 0x1U << 4 ) // UDC sent stall handshake
#define UDCCSR0_FST  ( 0x1U << 5 ) // Force the UDC to issue a stall handshake
#define UDCCSR0_RNE  ( 0x1U << 6 ) // There is unread data in the Rx FIFO
#define UDCCSR0_SA   ( 0x1U << 7 ) // Current packet in FIFO is part of UDC setup command

// UDC Endpoint Control/Status Registers A-X
#define UDCCSR_FS    ( 0x1U << 0 ) // FIFO needs service
#define UDCCSR_PC    ( 0x1U << 1 ) // Packet Complete
#define UDCCSR_TRN   ( 0x1U << 2 ) // Endpoint FIFO error
#define UDCCSR_DME   ( 0x1U << 3 ) // DMA Enable
#define UDCCSR_SST   ( 0x1U << 4 ) // Sent STALL
#define UDCCSR_FST   ( 0x1U << 5 ) // Force STALL
#define UDCCSR_BNE_BNF  ( 0x1U << 6 ) // Buffer not empty/full
#define UDCCSR_SP    ( 0x1U << 7 ) // Short Packet
#define UDCCSR_FEF   ( 0x1U << 8 ) // Flash Endpoint FIFO
#define UDCCSR_DPE   ( 0x1U << 9 ) // Data Packet Error

// UDC Endpoint A-X Configuration Registers
#define UDCCRZ_EE   ( 0x1U << 0 ) // Endpoint Enable
#define UDCCRZ_DE_SHIFT    1
#define UDCCRZ_DE   ( 0x1U << 1 ) // Double-buffering Enable
#define UDCCRZ_MPS_SHIFT 2
#define UDCCRZ_MPS_MASK    ( 0x3FFU << UDCCRZ_MPS_SHIFT) // Maximum Packet Size
#define UDCCRZ_ED_SHIFT    12
#define UDCCRZ_ED   ( 0x1U << 12 ) // Endpoint Direction
#define UDCCRZ_ET_SHIFT    13
#define UDCCRZ_ET_MASK     ( 0x3U << UDCCRZ_ET_SHIFT)  // Endoint Type
#define UDCCRZ_EN_SHIFT    15
#define UDCCRZ_EN_MASK     ( 0xFU << UDCCRZ_EN_SHIFT)  // Endoint Number
#define UDCCRZ_AISN_SHIFT  19
#define UDCCRZ_AISN_MASK   ( 0x7U << UDCCRZ_AISN_SHIFT)  // Interface Alternate Settings Number
#define UDCCRZ_IN_SHIFT    22
#define UDCCRZ_IN_MASK     ( 0x7U << UDCCRZ_IN_SHIFT)    // Interface Number
#define UDCCRZ_CN_SHIFT    25
#define UDCCRZ_CN_MASK     ( 0x3U << UDCCRZ_CN_SHIFT)    // Configuration Number

//#define XLLP_UDC_UDCCRZ_MPS_SHIFT 2
#define MAX_PKT_IN        (0x40 << 2)
#define MAX_PKT_BULK_8    (0x8  << 2)
#define MAX_PKT_BULK_16   (0x10 << 2)
#define MAX_PKT_BULK_32   (0x20 << 2)
#define MAX_PKT_BULK_64   (0x40 << 2)
#define MAX_PKT_ISO       (0x3FF << 2)

//#define XLLP_UDC_UDCCRZ_ED_SHIFT    12
#define EP_DIRECTION_IN   (0x1 << 12)
#define EP_DIRECTION_OUT  (0x0 << 12)

//#define XLLP_UDC_UDCCRZ_ET_SHIFT    13
#define EP_TYPE_INTERRUPT (0x3 << 13)
#define EP_TYPE_BULK      (0x2 << 13)
#define EP_TYPE_ISO       (0x1 << 13)

//Endpoints 1 - 15
//#define XLLP_UDC_UDCCRZ_EN_SHIFT    15
#define EP_NUM_1   (0x1  << 15)
#define EP_NUM_2   (0x2  << 15)
#define EP_NUM_3   (0x3  << 15)
#define EP_NUM_4   (0x4  << 15)
#define EP_NUM_5   (0x5  << 15)
#define EP_NUM_6   (0x6  << 15)
#define EP_NUM_7   (0x7  << 15)
#define EP_NUM_8   (0x8  << 15)
#define EP_NUM_9   (0x9  << 15)
#define EP_NUM_10  (0x10 << 15)
#define EP_NUM_11  (0x11 << 15)
#define EP_NUM_12  (0x12 << 15)
#define EP_NUM_13  (0x13 << 15)
#define EP_NUM_14  (0x14 << 15)
#define EP_NUM_15  (0x15 << 15)

//Alternate Interface Settings 0 - 7
//#define XLLP_UDC_UDCCRZ_AISN_SHIFT  19
#define ALTERNATE_INTERFACE_SETTING_0  (0x0 << 19)
#define ALTERNATE_INTERFACE_SETTING_1  (0x1 << 19)
#define ALTERNATE_INTERFACE_SETTING_2  (0x2 << 19)
#define ALTERNATE_INTERFACE_SETTING_3  (0x3 << 19)
#define ALTERNATE_INTERFACE_SETTING_4  (0x4 << 19)
#define ALTERNATE_INTERFACE_SETTING_5  (0x5 << 19)
#define ALTERNATE_INTERFACE_SETTING_6  (0x6 << 19)
#define ALTERNATE_INTERFACE_SETTING_7  (0x7 << 19)

//Interface Settings 0 - 7
//#define XLLP_UDC_UDCCRZ_IN_SHIFT    22
#define INTERFACE_SETTING_0  (0x0 << 22)
#define INTERFACE_SETTING_1  (0x1 << 22)
#define INTERFACE_SETTING_2  (0x2 << 22)
#define INTERFACE_SETTING_3  (0x3 << 22)
#define INTERFACE_SETTING_4  (0x4 << 22)
#define INTERFACE_SETTING_5  (0x5 << 22)
#define INTERFACE_SETTING_6  (0x6 << 22)
#define INTERFACE_SETTING_7  (0x7 << 22)

//Configuration Number 1-3
//#define XLLP_UDC_UDCCRZ_CN_SHIFT    25
#define CONFIG_NUM_1  (0x1 << 25)
#define CONFIG_NUM_2  (0x2 << 25)
#define CONFIG_NUM_3  (0x3 << 25)
#endif
